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motorola semiconductor technical data order number: mpc9229/d rev 1 03/2003 ? motorola, inc. 2003 400 mhz low voltage pecl clock synthesizer the mpc9229 is a 3.3v compatible, pll based clock synthesizer targeted for high performance clock generation in mid-range to high-performance telecom, networking and computing applications. with output frequencies from 25 mhz to 400 mhz and the support of differential pecl output signals the device meets the needs of the most demanding clock applications. features ? 25 mhz to 400 mhz synthesized clock output signal ? differential pecl output ? lvcmos compatible control inputs ? on-chip crystal oscillator for reference fr equency generation ? 3.3v power supply ? fully integrated pll ? minimal frequency overshoot ? serial 3-wire programming interface ? parallel programming interface for power-up ? 32 lead lqfp and 28 plcc packaging ? sige technology ? ambient temperature range 0 cto+70 c ? pin and function compatible to the mc12429 functional description the internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. the frequency of the internal crystal oscillator is divided by 16 and then multiplied by the pll. the vco within the pll operates over a range of 800 to 1600 mhz. its output is scaled by a divider that is configured by either the serial or parallel interfaces. the crystal oscillator fr equency f xtal , the pll feedback-divider m and the pll post-divider n determine the output frequency. the feedback path of the pll is internal. the pll adjusts the vco output frequency to be 4 ? m times the reference frequency by adjusting the vco control voltage. note that for some values of m (either too high or too low) the pll will not achieve phase lock. the pll will be stable if the vco frequency is within the specified vco frequency range (800 to 1600 mhz). the m-value must be programmed by the serial or parallel interface. the pll post-divider n is configured through either the serial or the parallel interfaces, and can provide one of four division ratios (1, 2, 4, or 8). this divider extends performance of the part while providing a 50% duty cycle. the output driver is driven differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 ? to v cc ?2.0v.the positive supply voltage for the internal pll is separated from the power supply for the core logic and output drivers to minimize noise induced jitter. the configuration logic has two sections: serial and parallel. the parallel interface uses the values at the m[8:0] and n[1:0] inputs to configure the internal counters. it is recommended on system reset to hold the p_load input low until power becomes valid. on the low?to?high transition of p_load , the parallel inputs are captured. the parallel interface has priority over the serial interface. internal pullup resistors are provided on the m[8:0] and n[1:0] inputs prevent the lvcmos compatible control inputs from floating. the serial interface centers on a fourteen bit shift register. the shift register shifts once per rising edge of the s_clock input. the serial input s_data must meet setup and hold timing as specified in the ac characteristics section of this document. the configuration latches will capture the value of the shift register on the high?to?low edge of the s_load input. see the programming section for more information. the test output reflects various internal node values, and is controlled by the t[2:0] bits in the serial data stream. in order to minimize the pll jitter, it is recommended to avoid active signal on the test output. fa suffix 32 lead lqfp package case 873a mpc9229 400 mhz low voltage clock synthesizer fn suffix 28--lead plcc package case 776
mpc9229 motorola timing solutions 2 figure 1. mpc9229 logic diagram gnd test vcc vcc gnd fout fout nc m[3] m[2] m[1] m[0] p_load nc n[1] n[0] m[8] m[7] m[6] m[5] m[4] s_clock s_load vcc_pll vcc_pll nc nc xtal_in 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 figure 2. mpc9229 28--lead plcc pinout (top view) vcc oe xtal_out xtal_in xtal_out s_load 16 s_data s_clock m[0:8] xtal pll ref fb vco 800-1600 mhz 00 01 10 11 0to 511 9-bit m-divider m-latch n-latch 10 -- 20 mhz t-latch 9 2 te s t 3 le 00 bit 5-13 bit 3-4 bit 0-2 14 bit shift register sync n[1:0] oe p/s 1 2 4 8 fout fout test v cc v cc p_load 4 oe 1 4 3 2 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 7 8 6 5 figure 3. mpc9229 32--lead lqfp pinout (top view) vcc xtal_out p_load oe m[0] m[1] m[2] m[3] fout fout gnd vcc test gnd s_clock n[1] n[0] m[8] m[7] m[6] m[5] m[4] s_data s_load vcc_pll nc nc xtal_in 11 s_data mpc9229 mpc9229
mpc9229 timing solutions 3 motorola table 1. pin configuration pin i/o default type function xtal_in, xtal_out analog crystal oscillator interface fout, fout output lvpecl differential clock output test output lvcmos test and device diagnosis output s_load input 0 lvcmos serial configuration control input. this inputs controls the loading of the configuration latches with the contents of the shift register. the latches will be transparent when this signal is high, thus the data must be stable on the high-to-low transition. p_load input 1 lvcmos parallel configuration control input. this input controls the loading of the configuration latches with the content of the parallel inputs (m and n). the latches will be transparent when this signal is low, thus the parallel data must be stable on the low-to-high transition of p_load . p_load is state sensitive s_data input 0 lvcmos serial configuration data input. s_clock input 0 lvcmos serial configuration clock input. m[0:8] input 1 lvcmos parallel configuration for pll feedback divider (m). m is sampled on the low-to-high transition of p_load. n[1:0] input 1 lvcmos parallel configuration for post-pll divider (n). n is sampled on the low-to-high transition of p_load oe input 1 lvcmos output enable (active high) the output enable is synchronous to the output clock to eliminate the possibility of runt pulses on the f out output. oe = l low stops f out in the logic low state (f out =l,fout =h) gnd supply supply ground negative power supply (gnd) v cc supply supply v cc positive power supply for i/o and core. all v cc pins must be connected to the positive power supply for correct operation vcc_pll supply supply v cc pll positive power supply (analog power supply) table 2. output frequency range and pll post-divider n n o d i i i o f 1 0 output division output frequency range 0 0 1 200 - 400 mhz 0 1 2 100 - 200 mhz 1 0 4 50 - 100 mhz 1 1 8 25 - 50 mhz
mpc9229 motorola timing solutions 4 table 3. general specifications symbol characteristics min typ max unit condition v tt output termination voltage v cc -2 v mm esd protection (machine model) 200 v hbm esd protection (human body model) 2000 v lu latch-up immunity 200 ma c in input capacitance 4.0 pf inputs ja lqfp 32 thermal resistance junction to ambient jesd 51-3, single layer test board jesd 51-6, 2s2p multilayer test board 83.1 73.3 68.9 63.8 57.4 59.0 54.4 52.5 50.4 47.8 86.0 75.4 70.9 65.3 59.6 60.6 55.7 53.8 51.5 48.8 c/w c/w c/w c/w c/w c/w c/w c/w c/w c/w natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min jc lqfp 32 thermal resistance junction to case 23.0 26.3 c/w mil-spec 883e method 1012.1 table 4. absolute maximum ratings a symbol characteristics min max unit condition v cc supply voltage -0.3 3.9 v v in dc input voltage -0.3 v cc +0.3 v v out dc output voltage -0.3 v cc +0.3 v i in dc input current 20 ma i out dc output current 50 ma t s storage temperature -65 125 c a. absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. functional operation at absolute-maximum-rated conditions is not implied. table 5. dc characteristics (v cc =3.3v 5%, t a =0 cto+70 c) symbol characteristics min typ max unit condition lvcmos control inputs (p_load , s_load, s_data, s_clock, m[0:8], n[0:1], oe) v ih input high voltage 2.0 v cc +0.3 v lvcmos v il input low voltage 0.8 v lvcmos i in input current a 200 a v in =v cc or gnd differential clock output f out b v oh output high voltage c v cc --1.02 v cc --0.74 v lvpecl v ol output low voltage c v cc --1.95 v cc --1.60 v lvpecl test and diagnosis output test v oh output high voltage c 2.0 v i oh =-0.8ma v ol output low voltage c 0.55 v i ol =0.8ma supply current i cc_pll maximum pll supply current 20 ma v cc_pll pins i cc maximum supply current 100 ma all v cc pins a. inputs have pull-down resistors affecting the input current. b. outputs terminated 50 ? to v tt =v cc -2v. c. the mpc9229 test output levels are compatible to the mc12429 output levels.
mpc9229 timing solutions 5 motorola table 6. ac characteristics (v cc =3.3v 5%, t a =0 cto+70 c) a symbol characteristics min typ max unit condition f xtal crystal interface frequency range 10 20 mhz f vco vco frequency range b 800 1600 mhz f max output frequency n = 00 ( 1) n=01( 2) n=10( 4) n=11( 8) 200 100 50 25 400 200 100 50 mhz mhz mhz mhz dc output duty cycle 45 50 55 % t r ,t f output rise/fall time 0.05 0.3 ns 20% to 80% f s_clock serial interface programming clock frequency c 0 10 mhz t p, mi n minimum pulse width (s_load, p_load ) 50 ns t s setup time s_data to s_clock s_clock to s_load m, n to p_load 20 20 20 ns ns ns t s hold time s_data to s_clock m, n to p_load 20 20 ns ns t jit(cc) cycle--to--cycle jitter n = 00 ( 1) n=01( 2) n=10( 4) n=11( 8) 90 130 160 190 ps ps ps ps t jit(per) period jitter n = 00 ( 1) n=01( 2) n=10( 4) n=11( 8) 70 120 140 170 ps ps ps ps t lock maximum pll lock time 10 ms a. ac characteristics apply for parallel output termination of 50 ? to v tt. b. the input frequency f xtal and the pll feedback divider m must match the vco frequency range: f vco =f xtal ? m 4. c. the frequency of s_clock is limited to 10 mhz in serial programming mode. s_clock can be switched at higher frequencies when used as test clock in test mode 6. see application section for more details.
mpc9229 motorola timing solutions 6 programming the mpc9229 programming the mpc9229 amounts to properly configuring the internal pll dividers to produce the desired synthesized frequency at the output. the output frequency can be represented by this formula: f out =(f xtal 16) ? (4 ? m) (4 ? n) or (1) f out =(f xtal 16) ? m n(2) where f xtal is the crystal frequency, m is the pll feedback-divider and n is the pll post-divider. the input frequency and the selection of the feedback divider m is limited by the vco-frequency range. f xtal and m must be configured to match the vco frequency range of 800 to 1600 mhz in order to achieve stable pll operation: m min =4 ? f vco,min f xtal and (3) m max =4 ? f vco,max f xtal (4) for instance, the use of a 16 mhz input frequency requires the configuration of the pll feedback divider between m=200 and m = 400. table 7 shows the usable vco frequency and m divider range for other example input frequencies. assuming that a 16 mhz input frequency is used, equation (2) reduces to: f out =m n(5) table 7. mpc9229 frequency operating range vco frequency for an crystal interface frequency of output frequency for f xtal =16 mhz and for n = m m[8:0] 10 12 14 16 18 20 1 2 4 16 160 010100000 800 170 010101010 850 180 010110100 810 900 190 010111110 855 950 200 011001000 800 900 1000 200 100 50 25 210 011010010 840 945 1050 210 105 52.5 26.25 220 011011100 880 990 1100 220 110 55 27.50 230 011100110 805 920 1035 1150 230 115 57.5 28.75 240 011110000 840 960 1080 1200 240 120 60 30 250 01111 1010 875 100 1125 1250 250 125 62.5 31.25 260 100000100 910 1040 1170 1300 260 130 65 32.50 270 100001110 810 945 1080 1215 1350 270 135 67.5 33.75 280 100011000 840 980 1120 1260 1400 280 140 70 35 290 100100010 870 1015 1160 1305 1450 290 145 72.5 36.25 300 100101100 900 1050 1200 1350 1500 300 150 75 37.5 310 100110110 930 1085 1240 1395 1550 310 155 77.5 38.75 320 101000000 800 960 1120 1280 1440 1600 320 160 80 40 330 101001010 825 990 1155 1320 1485 330 165 82.5 41.25 340 101010100 850 1020 1190 1360 1530 340 170 85 42.5 350 1010 11110 875 1050 1225 1400 1575 350 175 87.5 43.75 360 101101000 900 1080 1260 1440 360 180 90 45 370 101110010 925 1110 1295 1480 370 185 92.5 46.25 380 101111100 950 1140 1330 1520 380 190 95 47.5 390 110000110 975 1170 1365 1560 390 195 97.5 48.75 400 110010000 1000 1200 1400 1600 400 200 100 50 410 110011010 1025 1230 1435 420 110100100 1050 1260 1470 430 110101110 1075 1290 1505 440 110111000 1100 1320 1540 450 111000010 1125 1350 1575 510 111111110 1275 1530
mpc9229 timing solutions 7 motorola substituting n for the four available values for n (1, 2, 4, 8) yields: table 8. output frequency range for f xtal =16mhz n f out f out range f out step 1 0 value o u t o u t g o u t p 0 0 1 m 200 - 400 mhz 1mhz 0 1 2 m 2 100 - 200 mhz 500 khz 1 0 4 m 4 50 - 100 mhz 250 khz 1 1 8 m 8 25 - 50 mhz 125 khz example frequency calculation for an 16 mhz input frequency if an output frequency of 131 mhz was desired the following steps would be taken to identify the appropriate m and n values. according to table 8, 131 mhz falls in the frequency set by an value of 2 so n[1:0] = 01. for n = 2 the output frequency is f out =m 2 and m = f out x 2. therefore m = 2 x 131 = 262, so m[8:0] = 100000110. following this procedure a user can generate any whole frequency between 25 mhz and 400 mhz. note than for n > 2 fractional values of can be realized. the size of the programmable frequency steps (and thus the indicator of the fractional output frequencies achievable) will be equal to: f step =f xtal 16 n(6) using the parallel and serial interface the m and n counters can be loaded either through a parallel or serial interface. the parallel interface is controlled via the p_load signal such that a low to high transition will latch the information present on the m[8:0] and n[1:0] inputs into the m and n counters. when the p_load signal is low the input latches will be transparent and any changes on the m[8:0] and n[1:0] inputs will affect the fout output pair. to use the serial port the s_clock signal samples the information on the s_data line and loads it into a 14 bit shift register. note that the p_load signal must be high for the serial load operation to function. the test register is loaded with the first three bits, the n register with the next two and the m register with the final eight bits of the data stream on the s_data input. for each register the most significant bit is loaded first (t2, n1 and m8). a pulse on the s_load pin after the shift register is fully loaded will transfer the divide values into the counters. the high to low transition on the s_load input will latch the new divide values into the counters. figure 4 illustrates the timing diagram for both a parallel and a serial load of the mpc9229 synthesizer. m[8:0] and n[1:0] are normally specified once at power?up through the parallel interface, and then possibly again through the serial interface. this approach allows the application to come up at one frequency and then change or fine?tune the clock as the ab ility to control the serial interface becomes available. using the test and diagnosis output test the test output provides visibility for one of the several internal nodes as determined by the t[2:0] bits in the serial configuration stream. it is not configurable through the parallel interface. although it is possible to select the node that represents f out , the cmos output is not able to toggle fast enough for higher output frequencies and should only be used for test and diagnosis. the t2, t1 and t0 control bits are preset to ?000? when p_load is low so that the pecl fout outputs are as jitter?free as possible. any active signal on the test output pin will have detrimental affects on the jitter of the pecl output pair. in normal operations, jitter specifications are only guaranteed if the test output is static. the serial configuration port can be used to select one of the alternate functions for this pin. most of the signals available on the test output pin are useful only for performance verification of the mpc9229 itself. however the pll bypass mode may be of interest at the board level for functional debug. when t[2:0] is set to 110 the mpc9229 is placed in pll bypass mode. in this mode the s_clock input is fed directly into the m and n dividers. the n divider drives the f out differential pair and the m counter drives the test output pin. in this mode the s_clock input could be used for low speed board level functional test or debug. bypassing the pll and driving f out directly gives the user more control on the test clocks sent through the clock tree. figure 6 shows the functional setup of the pll bypass mode. because the s_clock is a cmos level the input frequency is limited to 200 mhz. this means the fastest the f out pin can be toggled via the s_clock is 100 mhz as the divide ratio of the post-pll divider is 2 (if n = 1). note that the m counter output on the test output will not be a 50% duty cycle. table 9. test and debug configuration for test t[2:0] test output t2 t1 t0 p 0 0 0 14-bit shift register out a 0 0 1 logic 1 0 1 0 f xtal 16 0 1 1 m-counter out 1 0 0 fout 1 0 1 logic 0 1 1 0 m-counter out in pll-bypass mode 1 1 1 fout 4 a. clocked out at the rate of s_clock table 10. debug configuration for pll bypass a output configuration f out s_clock n test m-counter out b a. t[2:0]=110. ac specifications do not apply in pll bypass mode b. clocked out at the rate of s_clock (4 ? n)
mpc9229 motorola timing solutions 8 figure 4. serial interface timing diagram s_clock s_data s_load m[8:0] n[1:0] p_load t2 t1 t0 n1 n0 m8 m7 m6 m5 m4 m3 m2 m1 m0 m, n first bit last bit power supply filtering the mpc9229 is a mixed analog/digital product. its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. random noise on the vcc_pll pin impacts the device characteristics. the mpc9229 provides separate power supplies for the digital circuitry (vcc) and the internal pll (vcc_pll) of the device. the purpose of this design technique is to try and isolate the high switching noise digital outputs from the relatively sensitive internal analog phase?locked loop. in a controlled environment such as an evaluation board, this level of isolation is sufficient. however, in a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. the simplest form of isolation is a power supply filter on the vcc_pll pin for the mpc9229. figure 5 illustrates a typical power supply filter scheme. the mpc9229 is most susceptible to noise with spectral content in the 1 khz to 1 mhz range. therefore, the filter should be designed to target this range. the key parameter that needs to be met in the final filter design is the dc voltage drop that will be seen between the vcc supply and the mpc9229 pin of the mpc9229. from the data sheet, the vcc_pll current (the current sourced through the vcc_pll pin) is maximum 20 ma, assuming that a minimum of 2.835 v must be maintained on the vcc_pll pin. the resistor shown in figure 5 must have a resistance of 10-15 ? to meet the voltage drop criteria. the rc filter pictured will provide a broadband filter with approximately 100:1 attenuation for noise whose spectral content is above 20 khz. as the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. the parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the pll. generally, the resistor/capacitor filter will be cheaper, easier to implement and provide an adequate level of supply filtering. a higher level of attenuation can be achieved by replacing the resistor with an appropriate valued inductor. a 1000 h choke will show a significant impedance at 10 khz frequencies and above. because of the current draw and the voltage that must be maintained on the vcc_pll pin, a low dc resistance inductor is required (less than 15 ? ). figure 5. v cc pll power supply filter vcc_pll v cc mpc9229 c 1 ,c 2 = 0.01...0.1 f v cc c f =22 f r f =10--15 ? c 2 c 1 layout recommendations the mpc9229 provides sub?nanosecond output edge rates and thus a good power supply bypassing scheme is a must. figure 6 shows a representative board layout for the mpc9229. there exists many different potential board layouts and the one pictured is but one. the important aspect of the layout in figure 6 is the low impedance connections between vcc and gnd for the bypass capacitors. combining good quality general purpose chip capacitors with good pcb layout techniques will produce effective capacitor resonances at frequencies adequate to supply the instantaneous switching current for the mpc9229 outputs. it is imperative that low inductance chip capacitors are used; it is equally important that the board layout does not introduce back all of the inductance saved by using the leadless capacitors. thin interconnect traces between the capacitor and the power plane should be avoided and multiple large vias should be used to tie the capacitors to the buried power planes. fat interconnect and large vias will help to minimize layout induced inductance and thus maximize the series resonant point of the bypass capacitors. note the dotted lines circling the crystal oscillator c onnection to the device. the oscillator is a series resonant circuit and the voltage amplitude across the crystal is relatively small. it is imperative that no actively switching signals cross under the crystal as crosstalk energy coupled to these lines could significantly impact the jitter of the device. special attention should be paid to the layout of the crystal to ensure a stable, jitter free interface between the crystal and the on?board osc illator. alt hough the mpc9229 has several design features to minimize the susceptibility to
mpc9229 timing solutions 9 motorola power supply noise (isolated power and grounds and fully differential pll), there still may be applications in which overall performance is being degraded due to system power supply noise. the power supply filter and bypass schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. figure 6. pcb board layout recommendation for the plcc28 package c2 1 c f xtal c1 c1 =v cc =gnd =via using the on--board crystal oscillator the mpc9229 features a fully integrated on--board crystal oscillator to minimize system implementation costs. the oscillator is a series res onant, multivibrator type design as opposed to the more common parallel resonant osc illator design. the series resonant design provides better stab ility and eliminates the need for large on chip capacitors. the oscillator is totally self contained so that the only external component required is the crystal. as the oscillator is somewhat sensitive to loading on its inputs the user is advised to mount the crystal as close to the mpc9229 as possible to avoid any board level parasitics. to fac ilitate co--location surface mount crystals are recommended, but not required. because the series resonant design is affected by capacitive loading on the xtal terminals loading variation introduced by crystals from different vendors could be a potential issue. for crystals with a higher shunt capacitance it may be required to place a resistance across the terminals to suppress the third harmonic. although typically not required it is a good idea to layout the pcb with the provision of adding this external resistor. the resistor value will typically be between 500 and 1k ? . the oscillator circuit is a series resonant circuit and thus for optimum performance a series resonant crystal should be used. unfortunately most crystals are characterized in a parallel resonant mode. fortunately there is no physical difference between a series resonant and a parallel resonant crystal. the difference is purely in the way the devices are characterized. as a result a parallel resonant crystal can be used with the mpc9229 with only a minor error in the desired frequency. a parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of osc illation a few hundred ppm lower than specified, a few hundred ppm translates to khz inaccuracies. in a general computer application this level of inaccuracy is immaterial. table 11 below specifies the performance requirements of the crystals to be used with the mpc9229. table 11. recommended crystal specifications parameter value crystal cut fundamental at cut resonance series resonance* frequency tolerance 75ppm at 25 c frequency/temperature stability 150pm 0 to 70 c operating range 0to70 c shunt capacitance 5--7pf equivalent series resistance (esr) 50 to 80 ? correlation drive level 100 w aging 5ppm/yr (first 3 years) * see accompanying text for series versus parallel resonant discussion.
mpc9229 motorola timing solutions 10 outline dimensions fn suffix plastic plcc package case 776--02 issue d notes: 1. datums --l--, --m--, and --n-- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum --t--, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. thepackagetopmaybesmallerthan thepackagebottombyupto0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). -- n -- -- m -- -- l -- v w d d y brk 28 1 view s s l--m s 0.010 (0.250) n s t s l--m m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l--m m 0.007 (0.180) n s t -- t -- b s l--m s 0.010 (0.250) n s t s l--m m 0.007 (0.180) n s t u s l--m m 0.007 (0.180) n s t z g1 x view d--d s l--m m 0.007 (0.180) n s t k1 view s h k f s l--m m 0.007 (0.180) n s t dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0 . 0 2 0 -- -- -- 0 . 5 1 -- -- -- k 0 . 0 2 5 -- -- -- 0 . 6 4 -- -- -- r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y -- -- -- 0 . 0 2 0 -- -- -- 0 . 5 0 z 210 210 g1 0.410 0.430 10.42 10.92 k1 0 . 0 4 0 -- -- -- 1 . 0 2 -- -- -- __ __
mpc9229 timing solutions 11 motorola outline dimensions fa suffix lqfp package case 873a-03 issue b 12 ref d1 d/2 e e1 1 8 9 17 25 32 f f e/2 detail g base c1 c b b1 metal section f--f e seating plane rr2 _ (s) l (l1) 0.25 gauge plane a2 a a1 detail ad detail ad d1/2 e1/2 e/2 4x d 7 a d b a--b 0.20 h 0.1 c (1) _ 8x a, b, d a--b m 0.20 d c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. datums a, b, and d to be determined at datum plane h. 4. dimensions d and e to be determined at seating plane c. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall not cause the lead width to exceed themaximumbdimensionbymorethan 0.08--mm. dambar cannot be located on the lower radius or the foot. minimum space between protrusion and adjacent lead or protrusion: 0.07--mm. 6. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is 0.25--mm per side. d1 and e1 are maximum plastic body size dimensions including mold mismatch. 7. exact shape of each corner is optional. 8. these dimensions apply to the flat section of the lead between 0.1--mm and 0.25--mm from the lead tip. dim min max millimeters a a1 7.00 bsc a2 0.80 bsc b 9.00 bsc b1 0.30 0.40 c 0.09 0.20 c1 0.09 0.16 d d1 e e e1 l l1 1.00 ref r1 0.08 0.20 r2 s 1 1.40 1.60 0.05 0.15 1.35 1.45 0.30 0.45 0 . 0 8 -- -- -- 07 __ _ 9.00 bsc 7.00 bsc 0.50 0.70 0.20 ref d 4x a--b 0.20 c d 6 6 4 4 detail g pin 1 index c 32x 28x h 5 8 plating 3 rr1
mpc9229 motorola timing solutions 12 information in this document is provided solely to enable system and software implementers to use motorola pr oducts. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee r egarding the suitability of its pr oducts for any particular purpose, nor does motorola assume any liab ility arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wit hout limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, inc luding ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems int ended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation wh ere personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hol d motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim a lleges that motorola was negligent regarding the design or manufacture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are the property of their respe ctive owners. e motorola inc. 2003 how to reach us: usa/europe/locations not listed : asia/pacific : motorola semiconductors h.k. ltd.; s ilicon har bour centre, 2, dai king street, tai po industrial estate, tai po, n.t., hong kong. technical information center: 852--26668334 1--800--521--6274 or 480--768--2130 home page : http://motorola.com/semiconductors japan : motorola japan ltd. ; sps, technical inf ormation center, 3--20--1, minami--azabu, minato--ku, tokyo 106--8573 japan 81--3--3440--3569 mpc9229/d ?

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